1. Field of the Invention
The present invention relates to a differential operational amplifier circuit, and more particularly to a high-gain and wide-band operational amplifier circuit.
2. Description of Related Art
As an example of differential operational amplifier circuits, an operational amplifier circuit composed of an input circuit including a differential transistor pair and an output circuit including a cascode circuit is described in “Analog Integrated Circuits and Signal Processing, vol. 18, pp. 21-31 (1999)” and “IEEE Journal of Solid-State Circuits, Vol. 30, No. 3, March 1995, pp. 166-172”. FIG. 2 is a circuit diagram showing the example of the operational amplifier circuit described in the above document. The operational amplifier circuit of FIG. 2 is composed of a wide-band differential input circuit including Nch transistors M1 to M4 and a differential output circuit including a cascode circuit of Nch transistors M5 to M8.
Gate electrodes of the Nch transistors M3 and M4 are connected with a common-mode feedback circuit (not shown) for setting a common-mode output voltage of the operational amplifier circuit. A simulation result of the operational amplifier circuit of FIG. 2 shows that a DC gain is 62 dB and a unity gain frequency is 450 MHz (no description about a load capacitance) provided that a semiconductor process with the minimum pitch of 0.5 μm is used, and a power supply voltage is 3 V.
The lowest operation voltage of an input circuit part of the operational amplifier circuit of FIG. 2 is determined based on the sum of a gate-source voltage VGS (for example, 0.6 V) of the Nch transistors M3 (or M4) and M5 (or M6) and a bias voltage necessary for the common-mode feedback circuit to drive a gate of the transistor M3 (or M4) (for example, saturation voltage of transistor, 0.25 V). This voltage is about 1.45 V (0.6 V×2+0.25 V) without consideration of variations. In contrast, the lowest operation voltage of an output circuit part is determined based on the sum of a saturation voltage (0.25 V) of each of the transistors M5, M7, M9, and M11 (or M6, M8, M10, and M12) and an output signal amplitude (for example, 0.5 V0-p). This voltage is about 1.5 V (0.25 V×4+0.5V) without consideration of variations.
In summary, the lowest operation voltage of the operational amplifier circuit of FIG. 2 is about 1.5 V as the lowest operation voltage of the output circuit part. A requisite nominal value of the lowest operation voltage is about 1.8 V in consideration of temperature characteristics or variations. Incidentally, as the transistors M3 and M4, non-doped Nch transistors that can set the gate-source voltage VGS to about 0.1 V can be used. In this case, the lowest operation voltage of the input circuit part can be lowered. However, a gate-source capacitance of the non-doped Nch transistor is very large and thus functions as a load of the input circuit part, leading to considerable deterioration of band characteristics of the operational amplifier circuit.
In the operational amplifier circuit of FIG. 2, a secondary pole is shifted to a low frequency side for obtaining a high DC gain in the input circuit part. If the secondary pole is shifted to the lower frequency side, there arises a problem that an operation of the operational amplifier circuit becomes unstable. Accordingly, in the operational amplifier circuit of FIG. 2, the DC gain needs to be increased only by the output circuit part for obtaining a high DC gain. As a result, the operational amplifier circuit of FIG. 2 has a drawback that the DC gain cannot be increased. If a gain boosting circuit is additionally provided, the output circuit part can improve the DC gain. However, this results in an increase in element area and power consumption.
Further, Japanese Unexamined Patent Application Publication No. 2000-151305 discloses a full differential operational amplifier circuit of a parallel path structure having a path of one amplifier stage and a path of two amplifier stages and synthesizing signals of the two paths at an output terminal. This full differential operational amplifier circuit enables high-gain and wide-band characteristics as well as operates at low power supply voltage.
The full differential operational amplifier circuit disclosed in Japanese Unexamined Patent Application Publication No. 2000-151305 enables a high gain by adding gains of the two signal amplifying paths. In this full differential operational amplifier circuit, one signal path is a two-stage amplifying path where an output of a first differential amplifier pair composed of Nch transistors is supplied to a gate electrode of a source-grounded Nch transistor after passing through a source to a drain of a gate-grounded Pch transistor, and a drain electrode of the Nch transistor is used as an output terminal. Further, the other signal path is a one-stage amplifying path where an output of a second differential amplifier pair composed of Nch transistors is connected with the output terminal after passing through a source to a drain of the gate-grounded Pch transistor. That is, a load of the Pch transistor and the gate-grounded Pch transistor exist in both of the two signal paths.
In general, a Pch transistor is inferior to an Nch transistor in frequency characteristics. Hence, the insertion of the Pch transistor to the signal amplifying path is undesirable in terms of wide-band characteristics.
To overcome such a problem, the applicants of the present invention discloses, in Japanese Patent No. 2004-015648 (hereinafter, referred to as “prior application”), an operational amplifier circuit of a parallel path structure including first and second differential transistor pairs where a resistor having one terminal applied with an intermediate potential through a source follower composed of a non-doped Nch transistor is set as a drain load with the first differential transistor pair set as an input circuit for a signal path of a gain path designed to have narrow-band and high-gain characteristics for increasing a DC gain and the second differential transistor pair set as an input circuit for a signal path of a feedforward path designed to have wide-band and low-gain characteristics for feedforward of the gain path to synthesize signals amplified via the paths at an output terminal.
According to the prior application, the lowest operation voltage can be set to 1.2 V without consideration of variations, and a nominal value of the lowest operation voltage can be set to about 1.5 V in consideration of variations. Further, if the gain path of the narrow-band and high-gain characteristics is parallel-connected with the forward path of the wide-band and low-gain characteristics, the characteristics of both the paths complement each other to thereby realize an operational amplifier circuit of high-gain and wide-band characteristics with a low power supply voltage.
According to the prior application, as operation voltages for the first differential amplifier circuit and the second differential amplifier circuit, intermediate potentials applied through the source follower circuit composed of the non-doped Nch transistor are used. Thus, a problem about reduction in power supply voltage down to about 1.5 V and a problem about reduction in frequency band for amplified differential signal components are solved. However, a channel width of the non-doped Nch transistor for generating a bias voltage needs to increase for operating the transistor at a power supply voltage lower than 1.5 V. Thus, there arises a problem that an area of the non-doped Nch transistor in a semiconductor chip increases, which hinders size reduction of the semiconductor chip.